As the gate length of transistors continues to shrink, the source (and/or drain) region(s) become(s) more of a factor in MOSFET (metal oxide semiconductor field effect transistor) performance. MOSFET scaling requires that the depth of the heavily doped regions at the source and/or drain be reduced, increasing the resistance of these regions relative to that of the channel. Furthermore, the geometry of the source/drain must be carefully engineered to avoid short-channel effects. These can most prominently be observed as high leakage currents in the off state.
There are a number of conventional techniques to address these issues of on-resistance and off-state leakage current. However, with virtually any design approach there are trade-offs between these two factors. For example, increasing the depth of a source region may reduce its on-resistance, but will increase the short-channel effects. Any solution typically seeks to optimize this trade-off based on the application.
In planar MOSFETs, the source and drain regions typically consist of implanted dopant atoms. To reduce the resistance of these regions, the dopant concentration can be increased. However, technological and physical limits to both the peak doping level and to the abruptness of doping profiles are limiting factors to MOSFET length scaling. See, e.g., M. Y. Kwong et al., “Impact of Lateral Source/Drain Abruptness on Device Performance”, IEEE Trans. Elec. Dev., vol. 49, pp. 1882-1890 (2002).
Another technique to reduce the source and/or drain resistance is the replacement of the implanted semiconductor regions forming the source and/or drain with a metal. Instead of a p-n junction, the metal forms a Schottky barrier at the interface to the channel. The resistance of the source and drain regions is then that of a metal, and not doped semiconductor, and hence may be orders of magnitude lower.
The limitation to such Schottky-barrier MOSFETs has been the resistance of the Shottky barrier that remains in the on-state of the transistor. See S. Sze, Physics of Semiconductor Devices 2nd ed. (1981), for a discussion of Schottky barriers. For example, ErSix has a barrier to the conduction band of Si of approximately 250 mV (see, M. Jang et al., “Schottky barrier tunnel transistor for nanometer regime applications”, 2003 Silicon Nanoelectronics Workshop Abstracts, pp. 114-115 (2003)), yielding poor drive current (high on-resistance) for n-channel MOSFETs. Similarly, PtSi has a barrier to the valence band of approximately 250 mV (see, J. Kedzierski et al., “Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime”, 2000 IEEE IEDM Tech. Digest, pp. 57-60 (2000)), increasing the on-resistance of p-channel MOSFETs.
When it comes to controlling short-channel effects, source/drain geometry becomes an important factor. Generally, it is desirable to make the source and drain regions much thinner than the length of the channel. In doped source/drain (S/D) transistors, this may be accomplished with shallow implants. A thin dopant layer may form a short “extension” between a deep, heavily doped source region and the (thin) channel. This has the effect of moving the deep source further from the channel to reduce the leakage current.
The challenge, and difficulty, is in making this dopant layer thinner while simultaneously increasing the doping density to keep the resistance within tolerable limits. The use of substrates such as silicon-on-insulator (SOI) may allow the doped source and drain to be kept thin by fabricating the transistor in a thin layer of Si, although ultra-thin SOI increases the problem of series resistance from doped Si. Schottky barrier MOSFETs may be fabricated using SOI to make very thin, yet low resistance, source and drain regions (again, at the possible expense of high on-resistance due to the Schottky barrier).
Geometries of a different sort may aid in decreasing the on-resistance of a Schottky barrier MOSFET. By overlapping the gate with the metal-semiconductor junction, the electric field between the source and/or drain and the gate can be used to increase the tunneling current through the barrier, lowering the on-resistance of the junction. This comes at the price of increased gate capacitance, however, which reduces switching speed. This also increases the short-channel effects.
Some of the above-described limitations may be overcome by creating an electrostatically induced extension between the source and/or drain contacts and the channel using so-called “side gate(s)”. That is, a conductor, separate from the gate and separated from the channel/source (drain) region (the so-called “extension region(s)”), may be used to induce an inversion layer, and/or enhanced accumulation layer, in the semiconductor when a voltage is applied to the conductor. This is similar to the action of the gate itself, and the extra conductor(s) may be thought of as isolated or side gate(s) on either side of the central gate forming the channel. These side gate(s) may be controlled separately from the gate.
An example of the use of side-gates was reported by Gonzalez et al., “A dynamic source-drain extension (DSDE) MOSFET using a separately biased conductive spacer”, Proceedings of 2001 International Semiconductor Device Research Symposium, pp. 645-648 (2001). FIG. 1 is a schematic cross-section of a transistor 10 incorporating the separately biased spacer technology described by Gonzalez et al. As shown, conductive spacers or side gates 12, separated from the gate 14 by an insulator 16 and from the source/drain regions 18 by a spacer oxide 20, induce a charge layer 22 (or “virtual extension”) that extends from the doped source/drain regions 18 to the channel 24 when a voltage is applied to the side gates 12. These charge layers 22 (more aptly termed “bias induced extensions” in this instance) may be very thin, approximately 2 nm, reducing short-channel effects in the MOSFET 10. They may also have a high carrier concentration, for low resistance. They may even have a higher concentration than the channel 24 in the on-state, depending on the capacitance, threshold voltage, and side gate voltage.
An earlier, experimental, demonstration of this approach, using polycrystalline Si side-gates, was published by Noda, et al. (IEEE Transactions on Electron Devices, v. 41, pp. 1831-1836, 1994). There are two main limitations to such a device, however. First, the added circuit complexity (e.g., the side gates 12 and the metal contacts required thereto) may be prohibitive. Second, the side-gate(s) 12 add significant capacitance to the gate 14, which will limit the speed of the transistor.
Another approach is to use the proximity of a conducting material to increase the carrier concentration in the extension region. This method was demonstrated by Parillo et al., as shown in FIG. 2. Doped polycrystalline Si spacers 28 connected to the source 30 (the source-side spacer) and the drain 32 (the drain-side spacer). See, Parillo et al., “The effect of biased spacers on LDD MOSFET behavior”, IEEE Elec. Dev. Lett., vol. 12, pp. 542-545 (1991). For doping in the spacers 28 of the appropriate type and of sufficient concentration, this can yield an enhanced carrier concentration in the extension regions 31 and 33 relative to that which would be present without the spacers. The authors also reported reduced electric fields in the vicinity of the drain 32 by using a SALICIDE (“Self ALigned silICIDE”) 34 over the source/drain spacer 28.
In transistor 26, the workfunction of the spacers 28 is near the workfunction of the extension region material (in this case Si). That is, the spacers 28 are not made of materials with workfunction significantly outside the Si bandgap; they are formed via TiSi (a mid-gap metal) on polycrystalline Si, hence a workfunction-induced extension is not formed in this device. Thus, while this approach may slightly enhance the conductivity of a traditional doped extension, it is not a substitute for a doped extension.
Bauernschmitt et al, “transition from MOS to Schottky-contact behaviour in Yb—SiO2—Si tunneling junctions with extremely thin SiO2 layer”, Microelectronic Engineering, vol. 22, pp. 105-108, (1993) described the use of Yb over thick SiO2 on Si to connect a Yb/SiO2/Si tunnel junction to an n+-doped contact. Yb's bulk workfunction is 2.6 V, according to the authors. The phenomenon of the tunneling of carriers between the metal and the workfunction-induced inversion layer was investigated at low temperature, and the characteristics of the Yb/thin SiO2/Si tunnel junction were examined.
A figure from Bauernschmitt's paper is reproduced as FIG. 3. In this device 36, the Yb at the Yb/SiO2 interface 38 induces an electron layer 40 near the Si/SiO2 interface 42, which connects the Yb/thin SiO2/Si tunnel junction 44 to the n+ Si region 46. The reported device is not a transistor, but rather a two-terminal test structure.
Kunze et al. “Observation of ID electron states at the boundary between an MOS and a Schottky contact on Si(100) by electron tunneling”, Surface Science vol. 305, pp. 633-636 (1994) formed workfunction-induced inversion layers in the vicinity of Mg/Si contacts, using Mg's low effective workfunction with SiO2. Schematic cross-sections from the paper are reproduced in FIG. 4.
Illustration 4(a) shows an idealized structure 48 with rectangular material sections. Electrostatic coupling from the Mg layer 50, only weakly pinned at its interface with the SiO2 layer 52, into the Si 54 yields a near-surface layer of electrons 56. Illustration 4(b) shows a more realistic structure 58, with the SiO2 layer 60 thinned near the Mg/Si contact 62. This results in electron tunneling through the thin region of the SiO2. Finally, illustration 4(c) shows a wider cross-section of the complete device 64. The workfunction-induced electron layer 66 connects the Mg/Si junction 62 to the source of this n-channel MOSFET.
Note the Mg induces an inversion layer in the Si, but this inversion layer is not between the source/drain contact 68/70 and the channel 72, and thus it is not serving as a virtual extension. There is some Mg overlap 74 of the SiO2 76 between the source/drain contact 68/70 and the channel 72, but the text of the article and its accompanying figures indicate is that this overlap is well within the region of the heavily doped source/drain. Thus, it fails to contribute significantly to the conductivity between the source/drain metal and the channel. For this overlap to be effective in increasing this conductivity, it should approach to within approximately 15 nm of the edge of the channel. See, D. Connelly et al., “Source/Drain Overlap for High-Performance Schottky S/D MOSFETs”, submitted to IEEE Nanotechnology Symposium, 2004, and D. Connelly et al., “Ultra-shallow MOSFET Extensions via Low or High Workfunction Metal Overlap”, submitted to IEEE VLSI Symposium, 2004. However, based on the description provided by the authors, this gap appears to be at least several micrometers—at least a factor 100 too large. Rather, the overlap is to provide a tolerance for misalignment for the metal definition photolithography relative to the preceding contact formation photolithography.
Tove et al. suggested the use of Er and Yb, both metals with effective workfunctions when in contact with SiO2 significantly outside the Si bandgap, as MESFET gates and S/Ds. P. A. Tove, et al., “Complementary Si MESFET Concept Using Silicon-on-Sapphire Technology”, IEEE Elec. Dev. Lett., vol. 9, pp. 47-49 (1988). A cross-section from their work is shown in FIG. 5. Devices 78 and 79 are not fabricated in a manner effective at inducing a virtual extension; indeed, the diagram indicates the low-workfunction (n-channel FET) and high-workfunction (p-channel FET) metals 80 and 82, respectively, do not overlap the SiO2 84, and thus the electrostatic coupling between these metals and the region between the contacts 81 and 83 and the channels is low. Strong electrostatic coupling is needed to substantially improve the conductivity in this region. Additionally, given the lateral scale of the devices it appears that there is a gap between the S/D metals 81 and 83 and the gate metals 80 and 82 of at least several micrometers. This is far too large a gap to form a high-conductivity virtual extension to the edge of the channel. For effective coupling to the channel, the virtual extension layer should extend to within approximately 15 nm of the channel. See, D. Connelly et al., IEEE VLSI Symposium, 2004 (submitted), supra.